Enhancing Chip Performance Through Predictive Analytics and Automated Design Verification

Abstract

Advancements in chip architecture and process technology have resulted in continued shrinkage of chip areas while integrating more and more functionality. Moreover, these chips are increasingly operating at higher performance and speed levels, often approaching thermal, power and reliability limits. This technical trend calls for new methodologies in the design verification of chips, especially in Exhaustive Detection of non-robust chips, since the costs of not detecting these chips early in their design life are becoming prohibitively expensive. This paper describes a systematic design methodology and new software tools that enable efficient use of predictive modelling and predictive analytics within the design cycle during implementation, compilation and verification. The predictive modelling relies on a combination of procedural and neural network based analytical models to estimate performance metrics early in the design cycle, preferably during synthesis. Then these predictive models are dynamically modified and further optimized during design compilation and data placement verification using a combination of predictive analytics and automated design convergence techniques to ensure chip quality-of-results.

In order to address the issue of Exhaustive Detection of thermal, power and thus reliability non-robust chips, we propose the design methodology and tools for verification that are crucial to the success of new Robust Design concepts, such as Adaptive Speed and Adaptive Voltage designs which are known to alleviate thermal and power non-robustness during normal chip operation. This paper illustrates the methodology with both analog and digital examples and discusses its implementation in a number of tools and systems.